Capacitance Ageing of Ceramic Capacitors

[PM3295]

"Capacitor ageing (Capacitance Drift) is a term used to describe the negative, logarithmic capacitance
change that takes place in ceramic capacitors with time. The ageing process has a negligible affect on
Class 1 (C0G) product but should be taken into account when measuring Class 2 (X7R, Y5V & Z5U)
product..".

"For Class 1 (C0G) ceramics the ageing rate is negligible. For Class 2 ceramics it may be necessary to
reset the ageing process..".

https://www.knowlescapacitors.com/getmedia/0d900fa3-87c5-4b78-aae5-ff6a837f1a3a/an0006
https://rfs.kyocera-avx.com/userFiles/uploads/pdfs/dielectric_aging.pdf

[Old_but_Alive]

I learned a lot today about decoupling capacitors.

I thought that parallel capacitors were good, for example 1uF/100nf/10nf across an IC pin was good

WRONG - it  creates a resonance.

search 

"Antiresonance of multiple parallel decoupling capacitors: use same value or multiple values?"
"Do chips really need multiple values of decoupling capacitor in the same packages?"

[PM3295]

Kemet has a nice simulator where you can play around with combinations of capacitor spice models.
https://ksim3.kemet.com/capacitor-simulation