ispLEVER Classic

[itp]

Hi All,

I am using ispLEVER Classic for programming Lattice GAL16V8d chip. I am new to this software.
I have following doubts.

1. How can I edit the  Constraint to decide the PINs.
2. How can I do PIN locking (This means physical pins should not change if I modify my code)
3. Any other software other than ispLEVER is available for this chips.

Thanks and regards
Itp

[avralam]

Use search button in this forum! Gal and pal

[harri_el_sucio]

hello itp:
Sorry for my language.

I programme in ABEL
And it is very simple
In the example later
In the list in Lenguage ABEL the arrow indicates the wished feet
Also the same thing can be done if you draw a scheme in ispLEVER Classic
Can send a simple scheme if you programme in scheme

Example:


MODULE Contador_binario_gray

TITLE 'Contador en Gray'



"Pins Input
clk, M, RESET pin 2, 3, 4;   <------------
"Pins Output
Z0, Z1, Z2 pin 17,18,19 istype 'pos, reg'; <-----------
"Status Register

SREG = [Z0, Z1, Z2];
S0 = [0,0,0];
S1 = [0,0,1];
S2 = [0,1,0];
S3 = [0,1,1];
S4 = [1,0,0];
S5 = [1,0,1];
S6 = [1,1,0];
S7 = [1,1,1];

equations

[Z0,Z1,Z2].clk= clk;
[Z0.ar, Z1.ar, Z2.ar] = RESET;

state_diagram SREG

state S0: goto S1;
state S1: if M then S3 else S2;
state S2: if M then S6 else S3;
state S3: if M then S2 else S4;
state S4: if M then S0 else S5;
state S5: if M then S4 else S6;
state S6: goto S7;
state S7: if M then S5 else S0;

test_vectors ([clk, RESET, M] -> [Z0, Z1, Z2])
[0,1,.X.] -> [0,0,0];
[.C.,0,0] -> [0,0,1];
[.C.,0,0] -> [0,1,0];
[.C.,0,1] -> [1,1,0];
[.C.,0,1] -> [1,1,1];
[.C.,0,1] -> [1,0,1];
[.C.,0,0] -> [1,1,0];
[.C.,0,0] -> [1,1,1];

[gem1144aaa]

hello itp:
Sorry for my language.

I programme in ABEL
And it is very simple
In the example later
In the list in Lenguage ABEL the arrow indicates the wished feet
Also the same thing can be done if you draw a scheme in ispLEVER Classic
Can send a simple scheme if you programme in scheme

Example:


MODULE Contador_binario_gray

TITLE 'Contador en Gray'



"Pins Input
clk, M, RESET pin 2, 3, 4;   <------------
"Pins Output
Z0, Z1, Z2 pin 17,18,19 istype 'pos, reg'; <-----------
"Status Register

SREG = [Z0, Z1, Z2];
S0 = [0,0,0];
S1 = [0,0,1];
S2 = [0,1,0];
S3 = [0,1,1];
S4 = [1,0,0];
S5 = [1,0,1];
S6 = [1,1,0];
S7 = [1,1,1];

equations

[Z0,Z1,Z2].clk= clk;
[Z0.ar, Z1.ar, Z2.ar] = RESET;

state_diagram SREG

state S0: goto S1;
state S1: if M then S3 else S2;
state S2: if M then S6 else S3;
state S3: if M then S2 else S4;
state S4: if M then S0 else S5;
state S5: if M then S4 else S6;
state S6: goto S7;
state S7: if M then S5 else S0;

test_vectors ([clk, RESET, M] -> [Z0, Z1, Z2])
[0,1,.X.] -> [0,0,0];
[.C.,0,0] -> [0,0,1];
[.C.,0,0] -> [0,1,0];
[.C.,0,1] -> [1,1,0];
[.C.,0,1] -> [1,1,1];
[.C.,0,1] -> [1,0,1];
[.C.,0,0] -> [1,1,0];
[.C.,0,0] -> [1,1,1];

Hi
Can you share your ABEL copy or send a link for it

[jack12345]

HI:

I found abel Links:http://www.elektroda.net/download/file201.html
However, I have not used!

[harri_el_sucio]

Hi : gem 1144aaa

The collector of ABEL this one included in ISPLever 5.1
The ISP Lever 5.1 that I use this one in :

http://www.sonsivri.com/forum/index.php?topic=4011.0
And OK works