review
http://www.xilinx.com/support/documentation/user_guides/ug332.pdf, page 58
probe cclk to see if you are seeing any clock distortion AT the prom pin
Or try setting the "configrate" on the bitstream generator to something slower
see:
ConfigRate: Bitstream Option for CCLK
For Master configuration mode, the ConfigRate bitstream generator option defines the
frequency of the internally-generated CCLK oscillator. The actual frequency is
approximate due to the characteristics of the silicon oscillator and varies by up to 50% over
the temperature and voltage range. On Spartan-3E and Extended Spartan-3A family
FPGAs, the resulting frequency for every ConfigRate setting is fully characterized and
specified in the associated FPGA family data sheet. At power-on, CCLK always starts
operation at its lowest frequency. Use the ConfigRate option to set the oscillator frequency
to one of the other values shown in Table 2-8.
Set this option graphically in “ISE Software Project Navigator,” page 42, as shown in Step 7
in Figure 1-7, page 44.
The FPGA does not start operating at the higher CCLK frequency
