Pic Logic analyzer board

[terval]

Hi, one board to make a very low cost, yet good Logic Analyzer, i found in web a good soft and i made serial port not usb, since it´s possible to use a usb > rs232.

Hope you like it.


Board:

http://rapidshare.com/files/227020490/Pic_La_Board.zip.html


Software:

http://pe1grl.khds.nl/picla/picla.htm


All the best to this forum.

[zawmintun1]

It Gone
Please upload in ifile or other

[koky]

direct download
http://pe1grl.khds.nl/picla/logan18.htm

[terval]

other link for board

http://ifile.it/o82nx7i

[raviraj]

reupload the files again

[samir]

can you mention it's technical specification if possible?

[titi]

Hello,

A short specification:

User selectable sampling of 2, 4 or 8 channels.
"Fast Sampling" at 5 MHz / 2 MHz / 1 MHz / 500 kHz, 200 kHz and 100 kHz giving resolutions of 200nSec to 10 uSec.
"Normal Sampling" at 500 kHz, 200 kHz, 100 kHz and 50 kHz giving resolutions of 2 uSec to 20 uSec.
3840, 7680 or 15360 samples can be stored in "Fast sampling" mode (depends on 8, 4 or 2 bit mode)
Also in the 500 kHz and slower rates the memory can be compressed, increasing the maximum capture time dramatically.

In "Normal Sampling" there is no limit to the duration of the trace, the current version supports up to 50 seconds.
A 256-Event burst buffer is used if the data lines change faster than the data can be transmitted to the PC
PC Link limits the "average" speed of the logic analyser (The nr. of transitions that can be recorded per second) in normal mode
Average limit for 8bit "Normal sampling": 3840 events/sec (115kBit) or 15000 events/sec (500kBit).
Average limit for 4bit "Normal sampling": 5760 events/sec (115kBit) or 25000 events/sec (500kBit).
Average limit for 2bit "Normal sampling": 11520 events/sec (115kBit) or 50000 events/sec (500kBit).

Best Regards.