Need urgent help for interfacing 89c51 and pic16f877

[aamir]

I am using pic16f877A microcomputer  in same circuit board pin 33 of PIC16F877A (configured as input)  is connected with  pin 13 of 89c51 (configured as output ) . pin no 13 of at89c51 microcontroller is connected with intr of pic 16f877a pin 33. when logic 1 is applied to 877a voltage on pin is 5 V but when logic 0 is applied, voltage is somewhere between 1.2v to 1.4 volts therefore some times 877a does not recognize interrupt.

[SONSiVRi]

I'd prefer better topic subject, so to let people know about your situation. This is stated in rules also.

Did you tried pull-down R?

[aamir]

Yes i HAVE PULL DOWN R

[SONSiVRi]

You might have enabled internal pull-ups?

Code:

RBPU (OPTION_REG<7>)

[zuisti]

Hi;
I think it's a program error. Check again the pin directions!
Seems the measured voltage (1.2-1.4 V) is a "floating" value: all both pins are inputs.
An other possible case: all pins are outputs and the 89c51 pin is too weak to pull down
the PIC's pin (emits logical 1) to zero.
zuisti

[oldvan]

...pin 33 of PIC16F877A (configured as input)  is connected with  pin 13 of 89c51 (configured as output )...

Assuming you are working with DIP40 packages, that would be RB0/INT of the 16F877 and P3.3 of the 89C51.

TRISB0 on the PIC needs to be set to 1 so that RB0 is an input,
and the equivelant needs set on the 89C51 so that P3.3 is an output.

...when logic 1 is applied to 877a voltage on pin is 5 V
but when logic 0 is applied, voltage is somewhere between 1.2v to 1.4 volts therefore some times 877a does not recognize interrupt.

Is this measured with a voltmeter, or with an oscilloscope?

Something maybe not so obvious but possibly causing the symptomsis the watchdog
timer on the PIC.  If it is enabled and not being cleared regularly, the PIC will
be resetting about every 18 mS, reverting the RB0 pin to an oputput until the code
changes it back to an input.  This could account for the measured voltage and be
the cause of erratic behavior.

Does the VDD rail have adequate decoupling capacitors to the VSS rail?