Signal your knowledge of the subject is surprising. I envy you very much. I feel very well your passion in this matter and I consider myself lucky to hear you speak. I have a lot, a lot to learn and I'm glad I met you. I promise you that I will try to annoy you as little as possible. I apologize in advance for any stupid question I do. Thanks so much.
First of all I have to say that you are also very good at drawing graphics and making the idea very well with drawing. I'm not as good as I am. The graphs are very clear and simple.
Perhaps I should start from this point: draw my idea in a simple and clear way, maybe 50% of the work takes place at this point.
We come to the point.
Most of the time I use the Half-Band filter, because for its structure it uses much less resources than another type of filter. Half of the coefficients is zero and the are symmetric, therefore it needs half of the multipliers. This was the main reason.
2) Filters on different cascades could be different - and even should be different for efficiency.
I agree, but until now efficiency was the least of my problems.
Polynomial interpolation is suitable for slow changing signal inside observed scope.
If I understand correctly it turns out to be good up to 0.4 * Fs. This is considered a slow signal. I am wrong ?
What happened between с and d ?
To get an "a" an interpolation filter uses x0, x1, x2, x3,
for "b" it uses x1, x2, x3, x4,
for "c" - x2, x3, x4, x5,
for "d" - x4, x5, x6, x7,
for "e" - x5, x6, x7, x8.
Excuse me so much but I misunderstood the question. I had just missed this thing, if I had grasped the question I would have arrived at the right answer. Now I notice the phenomenon perfectly.
Do you know what is the difference between and possible connection of interpolation of signal samples and interpolation of FIR filter coefficients ?
Honestly, the answer is not immediate as it could be for you. You can explain it to me simply ?
I expected a short answer that could be a sign of understanding. Much more words are required to reach that understanding. It is not optimal to spend time for it right now. Especially because I think that it is somehow cumulative understanding that will become clear itself later on this way.
Excuse me but still many things are obscure. Imagine yourself the first time you've heard of this subject. I am that person who knows even less than you at that moment.
You should practice in drawing such diagrams if you want to get it. How about interpolator with factor 5/3?
Thanks for the 3/2 diagrams example, now it's more clearer.
The diagram for 5/3 is this ?
Aha! We finally catch it!
I suppose that you are programmer.
Caught and sunk. Good boy. Actually I was born as a programmer. I started with the PIC16F84 a long time ago when it was not yet "Flash" but ROMless (PIC16C84), what good memories. Looking back on it now it was all much much simpler even though for the time it was the future. I then switched to PIC larger "PIC18" series starting to learn the "C" and then program them at a high level. All of a sudden I had to readjusted as an FPGA programmer (Xilinx) starting from less than zero, without even knowing what an FPGA was. So learning a bit of VHDL and even less of Verilog though it was very similar to "C", but I prefer VHDL. Continuing with a bit of VisualBasic, HTML, PHP, ASP, Python, Perl, SQL, Java, JavaScript, Bootstrap, Matlab, Linux, Linux Driver, to get up to C #. Surely I've forgotten someone. But among all these languages FPGA first and then the Signal Processing for me remain the ones I prefer. The complicated things fascinate me a lot and I try in every way to understand them despite being aware of my limitations. I never stop. So here I am trying to understand the Signal Processing associated with FPGA, one of the things that fascinates me and intrigues me the most. Thanks to you of course.
Imagine that you have a stream of data (samples) where only one of each 175 samples is not zero. How do you think, do you need to allocate memory to store all these zeros and perform actual computations upon them? I am curious is this clue enough for you?
Now that you make me think, excuse the term, it looks like a "bullshit". A very simple thing. I certainly do not need to memorize 175 zero values that I do not need at all, especially with a multiplication that will result is "zero".
It depends on what do you mean as structure. For example polyphase interpolator that uses one upsampler, one filter and one decimator could be coded as "one function" implementation for any factors:
out_samples_num = Resampler(
internal_resampler_context,
up_factor,
down_factor,
filter_coefficients,
filter_length,
filter_memory,
input_data,
input_data_size,
output_data_buf);
In that case for different factors you need different filters, but the same code.
Can the same value for a logical / hardware implementation in an FPGA ? I should keep the same hardware structure, at worst the main structure, and change the coefficients and/or the counter for the input/output samples.
(64/7) * (25/16) * 7 = 100
(64/8) * (25/16) * 8 = 100
(64/7) * 2 * (25/32) * 7 = 100
(64/8) * 2 * (25/32) * 8 = 100
(64/7) * 2 * (25/16) * (7/2) = 100
(64/8) * 2 * (25/16) * (8/2) = 100
(64/7) * 2 * (7/2) = 64
(64/8) * 2 * (8/2) = 64
(64/7) * 7 = 64
(64/8) * 8 = 64
Interpolators by 7/2 and 8/2 (and maybe 7 and 8 ) could share the same filter (the filter that passband is determined by factor 7 case while stopband - by factor 8 case). I expect non-significant compromise comparing with specialized filters for 7/2 and 8/2 factors. The wider gap between passband and stopband - the less tradeoff.
Note that interpolators with the same factor but in different lines above has different filters because of different input signals because of different processing stages before.
Sharing the same filter would be perfect. The structure for "7/2" could be used, where the band is wider. The passband and the stopband will be sufficient even for "8/2" where the band is narrower. I am wrong ?
By selecting this configuration
(64/7) * 2 * (25/16) * (7/2) = 100
(64/8) * 2 * (25/16) * (8/2) = 100
The useful max signal band is : 0.417 * Fs
[First half-band x 2]
"64/7"
9.142857 MHz ---> Fs/2 ---> 4.571428 MHz
Passband is 3.81 MHz (0.01 dB ripple) then Stopband is at 5.33 MHz (at least -60 dB)
"64/8"
8.000000 MHz ---> Fs/2 ---> 4.000000 MHz
Passband is 3.34 MHz (0.01 dB ripple) then Stopband is at 4.66 MHz (at least -60 dB)
The filter structure and coeffients is the same, use passband at 3.81 MHz and stop band at 5.33 MHz.
[Second half-band x 25/16]
18.285714 MHz ---> Fs/(25/16) ---> 28.571428 MHz
Passband is 3.81 MHz (0.01 dB ripple) then Stopband is at 24.76 MHz (at least -60 dB)
16.000000 MHz ---> Fs/(25/16) ---> 25.000000 MHz
Passband is 3.34 MHz (0.01 dB ripple) then Stopband is at 21.66 MHz (at least -60 dB)
The filter structure and coeffients is the same, use passband at 3.81 MHz and stop band at 21.66 MHz.
[Third selectable filter "7/2" or "8/2"]
28.571428 MHz ---> Fs/(7/2) ---> 100.000000 MHz
Passband is 3.81 MHz (0.01 dB ripple) then Stopband is at 96.19 MHz (at least -60 dB)
25.000000 MHz ---> Fs/(8/2) ---> 100.000000 MHz
Passband is 3.34 MHz (0.01 dB ripple) then Stopband is at 96.66 MHz (at least -60 dB)
For this filter I must use passband at 3.81 MHz and stop band at 96.19 MHz, however, the filter must be configurable according to the band selection.
In the last section, a polynomial interpolation could be used.
Did I understand well ?
And I did not say that you can not use Farrow filter or other type of polynomial interpolation on last stage. The choice has to be done after careful comparison of all variants under given target restrictions.
As you said precisely, I have restrictions mostly on the amount of multipliers to use. The maximum number should be 4 multipliers across the interpolation line, using a 200/250 MHz frequency, I do not think I can reach the 300 MHz frequency the device is very congested.
Patiently waiting ...
